M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 82

• Manufacturer Part Number: M30835FJGP#U3
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
. v
J
3
Table 7.3 RD, WRL and WRH Signals
NOTES:
Table 7.4 RD, WR and BHE Signals
0
2
7.2.3 Read and Write Signals
1
9
C
3 .
B
_________
When set to the 16-bit data bus, the PM02 bit in the PM0 register selects a combination of the RD, WR
and BHE signals or the RD, WRL and WRH signals to determine the read or write signal. When the DS3
to DS0 bits in the DS register are set to "0" (8-bit data bus), set the PM02 bit to "0" (RD/WR/BHE). If any
of the DS3 to DS0 bits are set to "1" (16-bit data bus) when accessing an 8-bit space, the combination of
_____
RD, WR and BHE is automatically selected regardless of the PM02 bit setting. Tables 7.3 and 7.4 list
each signal operations.
The RD, WR and BHE signals are combined for the read or write signal after reset.
When changing the combination to RD, WRL and WRH, set the PM02 bit before writing data to an
external memory.
When using the DRAMC to access the DRAM with the 16-bit bus, set the PM02 bit to "1" (RD/ WRL/
WRH).
8 /
0
Data Bus
1
1. The WR signal is used instead of the WRL signal.
Data Bus
0
16 Bits
3
8 Bits
16 Bits
3
8 Bits
J
________
G
4
a
______
_____
0 -
n
o r
3 .
1
_____
_____
u
______
, 1
3
______
p
1
2
(
0
M
________
______
0
________
3
6
2
C
RD
________
8 /
Page 57
H
H
H
H
L
L
L
L
, 3
RD
H
H
H
H
L
L
________
M
_________
_____
3
2
C
f o
________
8 /
WR
4
H
H
H
H
L
L
L
L
8
3
8
) T
WRL
H
L
H
H
L
L
(1)
(1)
_____
_________
Not used
Not used
BHE
H
H
________
L
L
L
L
________
Not used
Not used
WRH
H
H
L
L
H / L
H / L
_________
A
H
H
L
L
L
L
0
Read data
Write data to both even and odd addresses
Write 1-byte data to even address
Write 1-byte data to odd address
Write 1-byte data
Read 1-byte data
Write 1-byte data to odd address
Read 1-byte data from odd address
Read 1-byte data from even address
Read data from both even and odd addresses
Write 1-byte data
Read 1-byte data
Write 1-byte data to even address
Write data to both even and odd addresses
Status of External Data Bus
Status of External Data Bus
_____ ______ ________
_____
_____
________
______
7. Bus