M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 211

• Manufacturer Part Number: M30835FJGP#U3
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Figure 16.11 Transfer Clock Polarity
Figure 16.12 Transfer Format
2
0
16.1.1 Selecting CLK Polarity
16.1.2 Selecting LSB First or MSB First
C
1
9
3 .
B
8 /
As shown in Figure 16.11, the CKPOL bit in the UiC0 register (i=0 to 4) determines the polarity of the
transfer clock.
As shown in Figure 16.12, the UFORM bit in the UiC0 register (i=0 to 4) determines a data transfer format.
(1) When the CKPOL bit in the UiC0 register (i=0 to 4) is set to "0"
(2) When the CKPOL bit in the UiC0 register is set to "1"
0
1
3
0
(Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge)
(Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge)
3
J
G
4
a
o r
0 -
T
R
n
CLK
CLK
T
R
X
3 .
X
X
X
u
1
NOTES:
NOTES:
D
D
D
D
, 1
3
p
i
i
i
i
i
i
1. The CLKi pin is held high ("H") when no data is transferred.
2. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)
3. The CLKi pin is held low ("L") when no data is transferred.
4. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)
1
(
2
and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
M
and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
0
0
3
6
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
2
(1) When the UFORM bit in the UiC0 register (i=0 to 4) is set to "0"
NOTES:
R
CLK
T
R
CLK
T
C
NOTES:
X
X
X
X
2. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
D
D
8 /
D
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
D
Page 186
i
(LSB first)
i
i
i
i
i
transmitted on the falling edge of the transfer clock and received on the rising
edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
, 3
transmitted on the falling edge of the transfer clock and received on the rising
edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
D
D
D
D
0
0
0
0
M
3
2
D
D
D
D
C
1
1
f o
1
1
8 /
D
D
4
3
D
D
7
7
8
D
D
0
) T
D
0
D
8
2
2
2
2
D
D
D
D
D
D
6
6
D
D
1
1
3
3
3
3
D
D
D
D
5
5
D
D
2
D
2
D
4
4
4
4
D
D
D
D
4
4
D
D
D
3
D
3
5
5
5
5
D
D
D
D
D
D
D
D
3
3
4
4
6
6
6
6
D
D
D
D
D
D
D
D
2
2
5
5
7
7
7
7
16. Serial I/O (Clock Synchronous Serial I/O)
D
D
D
D
1
1
6
6
D
D
D
D
0
0
7
7