M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 98

• Manufacturer Part Number: M30835FJGP#U3
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Figure 8.8 PLC1 Register
2
0
1
9
C
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
n
o r
PLL Control Register 1
b7
3 .
NOTES:
1
u
, 1
3
p
b6
1. Rewrite the PLC1 register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. Rewrite the PLC1 register after the CM17 bit in the CM1 register is set to "0" (main clock) .
3. When the CM21 bit in the CM2 register is set to "0" (clock selected by the CM17 bit), if the PLC11 bit
4. Do not rewrite the PLC12 bit if the PLL clock is the CPU clock source.
1
2
(
is set to "1" before the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock divided-
by-2 or divided-by-3 becomes the clock source of the CPU clock and peripheral function clock.
M
0
b5
0
3
6
2
b4
C
8 /
b3
0
Page 73
, 3
b2
M
b1
3
2
C
b0
0
f o
8 /
4
(b7 - b4)
3
8
PLC11
PLC12
Symbol
) T
8
(b0)
(b3)
Bit
Symbol
PLC1
(1, 2)
Reserved Bit
PLL Clock Division
Enable Bit
PLL Clock Division
Switch Bit
Reserved Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
(4)
(3)
Address
0377
16
Set to "0"
0 : Divide-by-2
1 : Divide-by-3
Set to "0"
0 : Disables the PLL clock to be divided
1 : Enables the PLL clock to be divided
After Reset
XXXX 0000
Function
2
8. Clock Generation Circuit
RW
RW
RW
RW
RW