M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 235

• Manufacturer Part Number: M30835FJGP#U3
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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16.5 Special Mode 3 (GCI Mode)
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Table16.24 GCI Mode Specifications
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2
Clock Synchronization Function The CTSi pin inputs a trigger
NOTES:
In GCI mode, the external clock is synchronized with the transfer clock used in the clock synchronous serial
I/O mode.
Table 16.24 lists specifications of GCI mode. Table 16.25 lists registers to be used and settings. Tables
16.25 to 16.27 list pin settings.
Transfer Data Format
Transfer Clock
1
Transmit/Receive Start
Conditions
Interrupt Request
Generation Timing
Error Detection
9
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B
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to
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1
0
3
"1" (interrupt requested).
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Transfer data : 8 bits long
The CKDIR bit in the UiMR register (i=0 to 4) is set to "1" (external clock selected):
an input from the CLKi pin
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
When a trigger signal is applied to the CTSi pin under the following conditions:
Transmit interrupt timing can be selected from the followings:
Receive interrupt timing
Overrun error
• Set the TE bit in the UiC1 register to "1" (transmit enable)
• Set the RE bit in the UiC1 register to "1" (receive enable)
• The UiIRS bit in the UiC1 register is set to "0" (UiTB register empty) :
• The UiIRS bit is set to "1" (transmit completed):
This error occurs when the seventh bit of the next received data is read before reading the
• Set the TI bit in the UiC1 register to "0" (data in UiTB register)
UiRB register.
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when data is transferred from the UiTB register to the UARTi transmit register (transmission started)
when a data transmission from the UARTi transfer register is completed
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Specification
16. Serial I/O (Special Function)