M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 320

• Manufacturer Part Number: M30835FJGP#U3
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
2
Figure 21.38 G0CMP0 to G0CMP3 Registers, G1CMP0 to G1CMP3 Registers, G0MSK0 to G0MSK1
0
1
C
9
3 .
B
8 /
0
1
3
0
3
J
Group i Data Compare Register j (i=0,1; j=0 to 3)
G
b7
4
Group i Data Mask Register j (i=0,1; j=0,1)
a
Group i Transmit CRC Code Register (i=0,1)
b7
b15
b15
Group i Receive CRC Code Register (i=0,1)
0 -
n
o r
NOTES:
NOTES:
3 .
1
NOTES:
u
, 1
3
1. Set the GiMSK0 register to use the GiCMP0 register.
p
1. Calculation results are reset by setting the TE bit in the GiCR register to "0" (transmit disabled).
2. Transmit CRC calculation is performed with every bit of transmit data transmitted while the TCRCE
1
1. The calculation result is reset by setting the RCRCE bit in the GiERC register to "0" (not used). If the
2. The result is reset to the default value selected by the CRCV bit in the GiEMR register before
3. Receive CRC calculation occurs with every bit of transmit data transmitted while the RCRCE bit in
Set the GiMSK1 register to use the GiCMP1 register.
2
(
Default value is determined by setting the CRCV bit in the GiEMR register.
bit in the GiETC register is set to "1" (used).
M
0
the ACRC bit in the GiCMPj register is set to "1" (reset), the result is reset by matching the data in
the GiCMPj register with the received data.
reception starts.
the GiERC register is set to "1" (used).
0
3
b8
Registers, G1MSK0 to G1MSK1 Registers, G0TCRC to G1TCRC Registers, and
G0RCRC to G1RCRC Registers
6
2
b8
C
b7
b7
8 /
Page 295
, 3
M
3
b0
b0
b0
2
b0
C
f o
8 /
Result of the transmit CRC calculation
Data to be compared
Masked data for received data
Set bits not being compared to "1"
4
3
Result of the receive CRC calculation
8
Symbol
G0CMP0 to G0CMP3
G1CMP0 to G1CMP3
Symbol
G0TCRC, G1TCRC
) T
8
Symbol
G0MSK0,G0MSK1
G1MSK0,G1MSK1
Symbol
G0RCRC, G1RCRC
Function
Function
21. Intelligent I/O (Group 0, 1 Communication Function)
Address
00F0
0130
Address
00F9
Function
Address
00FB
16
16
16-
Address
00F4
0134
, 0131
, 00F1
00F8
16
16
16
Function
-00FA
(1,2)
, 00F5
, 0135
16
16
16
(1, 2, 3)
, 0132
, 0139
, 00F2
16
16
, 013B
16
16
16
16
-0138
, 0133
, 00F3
16
-013A
16
16
Setting Range
16
00
Setting Range
00
16
16 to
16 to
After Reset
Indeterminate
After Reset
Indeterminate
Indeterminate
FF
After Reset
Indeterminate
Indeterminate
FF
After Reset
0000
16
16
16
RW
RO
RW
RW
RW
RO
RW
RW