M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 278

IC M32C/83 MCU FLASH 144LQFP

M30835FJGP#U3

Manufacturer Part Number
M30835FJGP#U3
Description
IC M32C/83 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30835FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Quantity
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Part Number:
M30835FJGP#U3M30835FJGP
Manufacturer:
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Quantity:
20 000
Company:
Part Number:
M30835FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30835FJGP#U3M30835FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R
R
M
e
E
3
. v
J
2
Figure 21.5 G0BT to G3BT Register and G0BCR0 to G3BCR0 Register
0
Figures 21.5 to 21.15 show registers associated with the intelligent I/O base timer, the time measurement
function and waveform generation function. (For registers associated with the communication function, see
Figures 21.32 to 21.38, Figures 21.42 to 21.45, Figures 21.47 to 21.49.)
1
C
9
3 .
B
8 /
0
1
3
0
3
J
b15
G
Group i Base Timer Register (i=0 to 3)
4
a
0 -
n
o r
Group i Base Timer Control Register 0 (i=0 to 3)
NOTES:
b7
3 .
1
u
NOTES:
1. Each base timer stops only when the BCK1 to BCK0 bits in the GiBCR0 register are set to "00
2. The GiBT register reflects the value of the base timer with a delay of one half f
, 1
3
p
b6
1
1. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement, waveform gene-
2. This setting can be used only when the UD1 to UD0 bits in the GjBCR1 register (j=0, 1) of group 0
stopped). The base timer counts when the BCK1 to BCK0 bits are set to a value other than "00
When the BTiS bit in the BTSR register and the BTS bit in the GiBCR1 register are set to "0", the base
timer is reset continually, remaining set to "0000
counting" state. When either BTiS bit or BTS bit is set to "1", this state is cleared and counting starts.
2
(
M
0
b5
ration function), set the G0BCR0 register and G1BCR0 register to the same value.
or 1 are set to "10
"10
0
b8
3
6
2
2
b4
b7
" in other modes or in group 2 or 3.
C
Page 253
8 /
b3
, 3
b2
M
b1
3
b0
2
C
b0
2
f o
" (two-phase signal processing mode). Do not set the BCK1 to BCK0 bits to
8 /
When the base timer is counting:
When read, the value of the counter can be read.
When write, the counter starts counting from the
value written. When the base timer is reset, the
GiBT register is set to "0000
When the base timer is reset:
The GiBT register is set to "0000
value is indeterminate. No value is written
4
Symbol
3
8
BCK0
BCK1
DIV0
DIV1
DIV2
DIV3
DIV4
) T
Symbol
G0BT,G1BT
G2BT,G3BT
Bit
8
IT
Symbol
G0BCR0 to G3BCR0
Count Source
Select Bit
Count Source
Divide Ratio
Select Bit
Base Timer
Interrupt Select Bit
Function
Bit Name
Address
00E1
0161
16
16
16
". This, in effect, places the base timer in a "no
00E2
Address
- 0160
- 00E0
(2)
16
16
"
(1)
, 0122
b1
If setting value is n (n = 0 to 31),
count source is divided by 2(n + 1).
No division if n=31.
0 : Bit 15 overflows
1 : Bit 14 overflows
16,
0
0
1
1
(n=0) 0 0 0 0 0 : Divide-by-2
(n=1) 0 0 0 0 1 : Divide-by-4
(n=2) 0 0 0 1 0 : Divide-by-6
(n=30) 1 1 1 1 0 : Divide-by-62
(n=31) 1 1 1 1 1 : No division
16,
16
.
b0
0
1
0
1
" but the
01A1
: Clock stops
: Do not set to this value
: Two-phase pulse signal is applied
: f
0121
16
1
b6 b5 b4 b3 b2
, 0162
16
16
- 01A0
:
- 0120
(1)
16
(1)
.
, 01A2
16
16
Function
BT
16
0000
i cycle.
Setting Range
After Reset
Indeterminate
Indeterminate
After Reset
00
16
16
to FFFF
2
16
" (clock
2
".
(2)
RW
RW
21. Intelligent I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW

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