M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 332

• Manufacturer Part Number: M30835FJGP#U3
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
2
Figure 21.43 G2MR and G2CR Register
0
1
C
9
3 .
B
8 /
0
1
3
0
Group 2 SI/O Communication Mode Register
3
J
b7
G
Group 2 SI/O Communication Control Register
4
a
b7
NOTES:
0 -
n
o r
NOTES:
b6
3 .
1
b6
u
1. Run the base timer clock for one or more cycles after the GMD1 to GMD0 bits are set to "00
2. Set the GMD1 to GMD0 bits to "01
, 1
3
1. The group 2 base timer may be reset when rewriting the RE or IPOL bit. To avoid resetting, set the
p
b5
1
(communication unit reset).
the base timer clock is stopped.
b5
RST2 bit in the G2BCR1 register to "0" (no base timer reset by a reset request from the
communication function).
2
(
M
0
b4
0
b4
3
6
2
b3
b3
C
8 /
b2
Page 307
b2
, 3
b1
b1
M
b0
3
b0
2
C
(b5 - b3)
UFORM
f o
Symbol
CKDIR
GMD0
GMD1
Symbol
TXEPT
8 /
IRS
OPOL
Bit
IPOL
4
(b3)
RE
Symbol
G2MR
TE
Bit
RI
3
TI
8
Symbol
G2CR
) T
8
Communication Mode
Select Bit
Internal/External Clock
Select Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Transfer Format
Select Bit
Transmit Interrupt
Cause Select Bit
Transmit Enable Bit
Transmit Register
Empty Flag
Transmit Buffer
Empty Flag
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Receive Enable Bit
Receive Complete
Flag
ISTxD Output Polarity
Switch Bit
ISRxD Input Polarity
Switch Bit
2
" (clock synchronous serial I/O mode) or "10
Bit Name
Bit Name
(1)
Address
016A
Address
016B
16
16
21. Intelligent I/O (Group 0, 1 Communication Function)
1
0 : Transmit disabled
1 : Transmit enabled
0 : Data is in the transmit register
1 : No data is in the transmit register
0 : Data is in the G2TB register
1 : No data is in the G2TB register
0 : Receive disabled
1 : Receive enabled
0 : No data is in the G2RB register
1 : Data is in the G2RB register
0 : No inverse
1 : Inverse
0 : No inverse
1 : Inverse
b1
0
0
1
1
(during transmission)
(transmission is completed)
0 : Internal clock
1 : External clock
0 : LSB first
1 : MSB first
0 : No data is in the transmit buffer
1 : Transmission is completed
b0
0
1
0
1
: Communication unit is reset
: Clock synchronous serial I/O
: IE mode
: Do not set to this value
(The OER bit is set to "0")
mode
(2)
After Reset
00XX X000
Function
(2)
Function
After Reset
0000 X000
2
2
" (IE mode) while
2
(1)
2
"
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO