M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 150

• Manufacturer Part Number: M30835FJGP#U3
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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13. DMAC II
13.1 DMAC II Settings
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The DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which
transfers the sum of two data added by an interrupt request from any peripheral functions.
Table 13.1 lists specifications of the DMAC II.
Table 13.1 DMAC II Specifications
2
NOTES:
0
DMAC II Request Factor
Transfer Data
Transfer Block
Transfer Space
Transfer Direction
Transfer Mode
Chained Transfer Function Parameters (transfer count, transfer address and other information) are
End-of-Transfer Interrupt
Multiple Transfer Function
DMAC II can be made available by setting up the following registers and tables.
• RLVL register
• DMAC II Index
• Interrupt control register of the peripheral function causing a DMAC II request
• The relocatable vector table of the peripheral function causing a DMAC II request
• IRLT bit in the IIOiIE register (i = 0 to 11) if using the intelligent I/O or CAN interrupt
13.1.1 RLVL Register
C
1
9
Refer to 10. Interrupts for details on the IIOiIE register
3 .
B
8 /
1. When transferring a 16-bit data to destination address 0FFFF
2. The actual space where transfer can occur is limited due to internal RAM capacity.
When the DMAII bit is set to "1" (DMAC II transfer) and the FSIT bit to "0" (normal interrupt), the DMAC II
is activated by an interrupt request from any peripheral function with the ILVL2 to ILVL0 bits in the inter-
rupt control register set to "111
Figure 13.1 shows the RLVL register.
0
1
3
0
10000
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4
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0 -
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3 .
1
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, 1
3
16
p
1
Item
. The same transfer occurs when the source address is 0FFFF
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2
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0
0
3
6
2
C
8 /
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3
2
C
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ILVL0 bits are set to "111
• Data in memory is transferred to memory (memory-to-memory transfer)
• Immediate data is transferred to memory (immediate data transfer)
• Data in memory (or immediate data) + data in memory are transferred to
8 bits or 16 bits
64-Kbyte space in addresses 00000
Fixed or forward address
Single transfer, burst transfer
switched when transfer counter reaches zero
Interrupt occurs when a transfer counter reaches zero
Multiple data can be transferred by a generated request for one DMA II transfer
Interrupt requests generated by all peripheral functions when the ILVL2 to
8 /
Selected separately for each source address and destination address
memory (calculation transfer)
4
3
8
2
) T
8
" (level 7).
2
"
Specification
16
to 0FFFF16
16
, it is transferred to 0FFFF
16
.
(1, 2)
13. DMACII
16
and