M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 210

• Manufacturer Part Number: M30835FJGP#U3
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
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J
Figure 16.10 Transmit and Receive Operation
2
0
C
1
9
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
CTSi
CLKi
TxDi
TXEPT bit in
UiC0 register
IR bit in SiTIC
register
3 .
(1) Transmit Timing (Internal clock selected)
B
8 /
The above applies to the following settings:
0
1
• The CKDIR bit in the UiMR register is set to "0" (internal clock selected)
• The CRD bit in the UiC
• The CKPOL bit the in UiC
• The UiIRS bit in the UiC
OER bit in UiRB
register
IR bit in SiRIC
register
RE bit in UiC1
register
TE bit in UiC1
register
TI bit in UiC1
register
RTSi
CLKi
RxDi
RI bit in UiC1
register
3
(2) Receive Timing (External clock selected)
f
0
The CRS bit is set to "0" (CTS function selected)
falling edge of the transfer clock)
The above applies to the following settings:
EXT
3
• The CKDIR bit in the UiMR register is set to "1" (external clock selected)
• The CRD bit in the UiC
• The CKPOL bit in the UiC0 register is set to "0"
J
G
The CRS bit is set to "1" (RTS function selected)
(Data is received on the rising edge of the transfer clock)
4
a
: External clock frequency
o r
0 -
n
3 .
1
u
, 1
3
p
1
(
2
M
0
"H"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"L"
0
3
6
2
"H"
"1"
"0"
"1"
"0"
"1"
"0"
"L"
"1"
"0"
"1"
"0"
"1"
"0"
C
8 /
Page 185
0
1
Data is set in the UiTB register
register is set to "0" (RTS/CTS function enabled)
Data transferred from UARTi register to UiRB register
, 3
0
register is set to "0" (no data in the UiTB register)
0
register is set to "0" (data transmitted on the
register is set to "0" (RTS/CTS function enabled)
D
M
0
3
i=0 to 4
Data is transferred from the UiTB register to the UARTi transmit register
D
2
1
D
C
0
f o
T
D
8 /
CLK
D
2
1
4
3
Dummy data is set in the UiTB register
D
8
3
D
) T
8
2
D
Tc
4
D
3
D
5
D
Set to "0" by an interrupt request acknowledgement or by program
4
1 / f
D
Set to "0" by an interrupt request acknowledgement or by program
Received data is taken in
6
D
5
EXT
D
7
D
Pulse stops because CTSi = H
6
Data is transferred from the UiTB register to the UARTi transmit register
D
7
D
0
D
1
D
0
Read by the UiRB register
D
2
D
Becomes "L" when the UiRB register is read
T
NOTES:
1
D
C
1. The CNT3 to CNT0 bits in the TCSPR register select no division (
3
=2(m+1)/fj
D
fj : Count source frequency set in the UiBRG register (f
m : Setting value of the UiBRG register
2
i = 0 to 4
n=0) or divide-by-2n (n=1 to 15).
D
Meet the following conditions while "H" is applied to the CLKi
pin before receiving data:
4
D
• Set the TE bit in the UiC
• Set the RE bit in the UiC
• Write dummy data to the UiTB register
3
D
16. Serial I/O (Clock Synchronous Serial I/O)
5
D
4
D
6
D
5
D
7
D
6
Pulse stops because TE bit = 0
D
7
D
0
D
0
D
1
1
1
D
register to "1" (transmit enable)
register to "1" (receive enable)
1
D
2
D
2
D
3
D
3
D
4
D
4
D
5
D
5
D
6
D
6
D
7
1
, f
8
, f
2n (1)
)