AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 123
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AT91RM9200-CI-002
Manufacturer Part Number
AT91RM9200-CI-002
Description
IC ARM9 MCU 256 BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91RM9200-EK.pdf
(41 pages)
2.AT91RM9200-DK.pdf
(2 pages)
3.AT91RM9200-QU-002.pdf
(701 pages)
Specifications of AT91RM9200-CI-002
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
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16.3
16.3.1
16.3.2
1768I–ATARM–09-Jul-09
Functional Description
Bus Arbiter
Address Decoder
The Memory Controller (MC) handles the internal ASB bus and arbitrates the accesses of up to
four masters.
It is made up of:
The Memory Controller handles only little-endian mode accesses. All masters must work in little-
endian mode only.
The Memory Controller has a user-programmable bus arbiter. Each master can be assigned a
priority between 0 and 7, where 7 is the highest level. The bus arbiter is programmed in the reg-
ister MC_MPR (Master Priority Register).
The same priority level can be assigned to more than one master. If requests occur from two
masters having the same priority level, the following default priority is used by the bus arbiter to
determine the first to serve: Master 0, Master 1, Master 2, Master 3.
The masters are:
The Memory Controller features an Address Decoder that first decodes the four highest bits of
the 32-bit address bus and defines 11 separate areas:
• A bus arbiter
• An address decoder
• An abort status
• A misalignment detector
• the ARM920T as the Master 0
• the Peripheral DMA Controller as the Master 1
• the USB Host Port as the Master 2
• the Ethernet MAC as the Master 3
• One 256-Mbyte address space for the internal memories
• Eight 256-Mbyte address spaces, each assigned to one of the eight chip select lines of the
• One 256-Mbyte address space reserved for the embedded peripherals
• An undefined address space of 1536M bytes that returns an Abort if accessed
External Bus Interface
AT91RM9200
123
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