AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 675

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

41.6.3
41.6.4
41.7
1768I–ATARM–09-Jul-09
ROM Bootloader
PMC, Clock Generator: Bad switching when writing PLL registers with same MUL and DIV values
OSCBYPASS is not functional with PLLA
the ones already stored, the status bit MCKRDY does not rise. When one and only one of the
fields PRES and CSS is changed, the MCKRDY bit operates normally.
Problem Fix/Workaround
If both fields must be re-programmed, carry out the change in two steps.
When the fields MUL and DIV in the CKGR_PLLBR register are written with the same values as
already programmed, the Master Clock signal switches to Main Clock (output of the Main Oscil-
lator) until a different value is programmed in the register.
When the fields MUL and DIV in the CKGR_PLLAR register are written with the same values as
already programmed, the Master Clock signal switches to Slow Clock (output of the 32768 Hz
Oscillator) until a different value is programmed in the register.
Problem Fix/Workaround
The user must be sure that either the DIV or MUL field changes when setting the CKGR_PLLBR
or CKGR_PLLAR register.
With PLLA, it is not possible to have an MCKRDY flag raised.
Problem Fix/Workaround
Even if MCKRDY flag does not raise with PLLA, it will not prevent you from switching on it.
You just need to wait for the PLLA lock time; for that program, PLLA then PLLB. When PLLB is
ready, PLLA is ready too.
Main Oscillator in Bypass Mode: CKGR_MOR = 0x00000002
PLLA programming: CKGR_PLLAR = 0x20063E01
PLLB programming: CKGR_PLLBR = 0x10173F05
Wait PLLB LOCKB bit: PMC_SR will be 0x0000000C
Switch on PLLACK clock: PMC_MCKR -> 0x00000102
PMC_SR will be 0x0000000C
ROM Bootloader: Limitation with 8-bit parallel memories.
Limitation with 8-bit parallel memories. In the internal Boot Rom program, version 1.0, the wait
state number on CS0 is set to 0 during Boot ROM initialization. This gives an access time of 20
ns at 48 MHz Master Clock Frequency. This limitation of the ROM Bootloader applies to
AT91RM9200 with the product number 58A07F.
Problem Fix/Workaround
None.
AT91RM9200
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