AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 295

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

24.5.3
24.5.4
1768I–ATARM–09-Jul-09
Watchdog Timer (WDT)
Real-time Timer (RTT)
Figure 24-3. Period Interval Timer
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in
a deadlock. It is built around a 16-bit down counter loaded with the value defined in ST_WDMR
(Watchdog Mode Register).
At reset, the value of the ST_WDMR is 0x00020000, corresponding to the maximum value of the
counter.
It uses the Slow Clock divided by 128 to establish the maximum watchdog period to be 256 sec-
onds (with a typical slow clock of 32.768 kHz).
In normal operation, the user reloads the Watchdog at regular intervals before the timer overflow
occurs, by setting the bit WDRST in the ST_CR (Control Register).
If an overflow does occur, the watchdog timer:
Writing the ST_WDMR does not reload or restart the down counter. When the ST_CR is written
the watchdog counter is immediately reloaded from ST_WDMR and restarted and the Slow
Clock 128 divider is also immediately reset and restarted.
Figure 24-4. Watchdog Timer
The Real-Time Timer is used to count elapsed seconds. It is built around a 20-bit counter fed by
Slow Clock divided by a programmable value. At reset, this value is set to 0x8000, correspond-
ing to feeding the real-time counter with a 1 Hz signal when the Slow Clock is 32.768 Hz. The
20-bit counter can count up to 1048576 seconds, corresponding to more than 12 days, then roll
over to 0.
The Real-Time Timer value can be read at any time in the register ST_CRTR (Current Real-time
Register). As this value can be updated asynchronously to the master clock, it is advisable to
read this register twice at the same value to improve accuracy of the returned value.
• Sets the WDOVF bit in ST_SR (Status Register), from which an interrupt can be generated.
• Generates an internal reset if the parameter RSTEN in ST_WDMR is set.
• Reloads and restarts the down counter.
SLCK
1/128
Slow Clock
SLCK
Down Counter
16-bit Down
16-bit
WDRST
Counter
PIV
WV
RSTEN
PITS
AT91RM9200
WDOVF Status
Internal Reset
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