AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 464

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

31.6.5.1
31.6.5.2
31.6.6
464
AT91RM9200
Data Format
Frame Sync Data
Frame Sync Edge Detection
If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and
SSC_TFMR programs the length of the pulse, from 1-bit time up to 16-bit time.
The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed
through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.
Frame Sync Data transmits or receives a specific tag during the Frame Synchro signal.
During the Frame Sync signal, the Receiver can sample the RD line and store the data in the
Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register
in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal
is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR.
Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or
lower than the delay between the start event and the actual data reception, the data sampling
operation is performed in the Receive Sync Holding Register through the Receive Shift Register.
The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync
Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than
the delay between the start event and the actual data transmission, the normal transmission has
priority and the data contained in the Transmit Sync Holding Register is transferred in the Trans-
mit Register then shifted out.
T h e F r a m e S y n c E d g e d e t e c t i o n i s p r o g r a m m e d b y t h e F S E D G E f i e l d i n
SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status
Register (SSC_SR) on frame synchro edge detection (signals RF/TF).
The data framing format of both the transmitter and the receiver are largely programmable
through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode
Register (SSC_RFMR). In either case, the user can independently select:
• The event that starts the data transfer (START).
• The delay in number of bit periods between the start event and the first data bit (
• The length of the data (DATLEN)
• The number of data to be transferred for each start event (DATNB).
• The length of Synchronization transferred for each start event (FSLEN).
• The bit sense: most or lowest significant bit first (MSBF).
Additionally, the transmitter can be used to transfer Synchronization and select the level
driven on the TD pin while not in data transfer operation. This is done respectively by the
Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in
SSC_TFMR.
1768I–ATARM–09-Jul-09
STTDLY
).