AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 466

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AT91RM9200-CI-002

Manufacturer Part Number
AT91RM9200-CI-002
Description
IC ARM9 MCU 256 BGA
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91RM9200-CI-002

Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
AT91RM9200-CI-002
Manufacturer:
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Quantity:
10 000
31.6.7
31.6.8
31.7
466
SSC Application Examples
AT91RM9200
Loop Mode
Interrupt
Figure 31-14. Receive Frame Format in Continuous Mode
Note:
The receiver can be programmed to receive transmissions from the transmitter. This is done by
setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is
connected to TF and RK is connected to TK.
Most bits in SSC_SR have a corresponding bit in interrupt management registers.
The SSC Controller can be programmed to generate an interrupt when it detects an event. The
Interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt
Disable Register), which respectively enable and disable the corresponding interrupt by setting
and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the
generation of interrupts by asserting the SSC interrupt line connected to the AIC.
Figure 31-15. Interrupt Block Diagram
The SSC can support several serial communication modes used in audio or high speed serial
links. Some standard applications are shown in the following figures. All serial link applications
supported by the SSC are not listed here.
1. STTDLY is set to 0.
TXBUFE
ENDTX
RXBUFF
ENDRX
PDC
RD
Transmitter
Receiver
Start = Enable Receiver
TXEMPTY
TXSYNC
RXSYNC
OVRUN
To SSC_RHR
TXRDY
RXRDY
DATLEN
Data
SSC_IER
To SSC_RHR
Set
DATLEN
SSC_IMR
Data
Interrupt
Control
SSC_IDR
Clear
SSC Interrupt
1768I–ATARM–09-Jul-09

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