AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 674

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

41.4.11
41.5
41.5.1
41.5.2
41.6
41.6.1
41.6.2
674
PIO
PMC
AT91RM9200
Data write operation and number of bytes
NWAIT activity depends on use of PC6
Output Data Status Register is always Read/Write
Constraints on the Master Clock selection sequence
MCKRDY does not rise in some cases
Problem Fix/Workaround
It consists in doing a software reset if RXRDY = 1 after the STOP_COMMAND. This flag indi-
cates that the MMCI receives more data than the PDC has been settle to transfer. After this soft
reset the MCI_CR, MCI_MR, MCI_DTOR, MCI_SDCR need to be reassigned.
The Data Write operation with a number of bytes less than 12 is impossible.
Problem Fix/Workaround
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The
BLKLEN or BCNT field are used to specify the real count number.
NWAIT activity depends on use of PC6. The PC6 line multiplexes with the NWAIT function. As
the PIO Controller is transparent in input, the level on the PC6 line has direct impact on the
behavior of the EBI. In particular, driving the PC6 line to 0 might lead to a deadlock of the
system.
Problem Fix/Workaround
Use PC6 carefully. In general, it is recommended to not use PC6 and to make sure the pull-up is
enabled.
The programming of the register PIO_OWSR has no effect on the read/write features of
PIO_ODSR, which is always read/write accessible.
Problem Fix/Workaround
None.
The PMC_MCKR register must not be programmed in a single write operation.
Problem Fix/Workaround
The preferred programming sequence for the PMC_MCKR register is as follows:
An exception to this sequence occurs when the processor clock frequency is greater than the
master clock frequency. In this case, the PRES field should be written first.
When re-programming the Master Clock Register, if both fields PRES and CSS are written with
the same values as the ones already stored, or if both fields are written with different values than
1. Program the CSS field in the PMC_MCKR.
2. Wait for the MCKRDY bit to be set in the PMC_SR register.
3. Program the PRES field (in the PMC_MCKR).
1768I–ATARM–09-Jul-09