AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 223

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Figure 20-7. Burst Suspend and Resume with Clock Control Address Advance
20.6.4.3
1768I–ATARM–09-Jul-09
Selection Signal
Internal BFC
BFAVD
A[24:0]
D[15:0]
D[15:0]
Output
BFWE
BFOE
BFCS
BFCK
Input
Burst Suspension for Transfer Enabling
(1) Only if Multiplexed Address & Data Buses
Burst Suspend and Resume (BFOEH = 1)
Clock Control Address Advance (BAAEN = 0)
The BFC can suspend a burst to enable other internal transfers, or other memory controllers to
use the memory address and data busses if they are shared. Two modes are provided on the
BFOEH bit (Burst Flash Output Enable Handling,
page
Address (1)
• BFOEH = 1: the BFC suspends the burst when it is no longer selected and the BFOE pin is
• BFOEH = 0: the BFC suspends the burst when it is no longer selected and the BFOE pin is
deasserted. When a new sequential access on the Burst Flash device is requested, the burst
is resumed and the BFOE pin is asserted again. The data is available on the data bus after
OEL cycles. This mode provides a minimal access latency. (Refer to
and
deasserted. When a new access to the Burst Flash device is requested, either sequential or
not, a new burst is initialized and the next data is available as defined by the AVL latency field
in the Mode Register. This mode is provided for Burst Flash devices for which the deassertion
of the BFOE signal causes an irreversible break of the burst.
the access request to the BFC and the deassertion of the BFOE signal due to a deselection
Address (D0)
227.):
Figure 20-7
AVL
above).
Sampling
D0
D0
Sampling
D1
D1
Sampling
D2
D2
Sampling
D3
D3
D4
See “Burst Flash Controller Mode Register” on
Address Valid Latency = 4 BFCK cycles (AVL = 3)
Output Enable Latency (OEL) = 2 BFCK cycles
Burst Suspend
Figure 20-8 on page 224
OEL = 2
AT91RM9200
Figure 20-6 on page 222
Sampling
Burst Resume
D4
D4
Sampling
D5
D5
D6
shows
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