AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 564
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AT91RM9200-CI-002
Manufacturer Part Number
AT91RM9200-CI-002
Description
IC ARM9 MCU 256 BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91RM9200-EK.pdf
(41 pages)
2.AT91RM9200-DK.pdf
(2 pages)
3.AT91RM9200-QU-002.pdf
(701 pages)
Specifications of AT91RM9200-CI-002
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
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AT91RM9200
Figure 34-9. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints
When using a ping-pong endpoint, the following procedures are required to perform Data OUT
transactions:
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO
3. The USB device sends an ACK PID packet to the host. The host can immediately send
4. The microcontroller is notified that the USB device has received a data payload, polling
5. The number of bytes available in the FIFO is made available by reading RXBYTECNT
6. The microcontroller transfers out data received from the endpoint’s memory to the
7. The microcontroller notifies the USB peripheral device that it has finished the transfer
8. A third Data OUT packet can be accepted by the USB peripheral device and copied in
9. If a second Data OUT packet has been received, the microcontroller is notified by the
10. The microcontroller transfers out data received from the endpoint’s memory to the
11. The microcontroller notifies the USB device it has finished the transfer by clearing
12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO
Bank 0.
a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1.
RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this
endpoint while RX_DATA_BK0 is set.
in the endpoint’s UDP_CSRx register.
microcontroller’s memory. Data received is made available by reading the endpoint’s
UDP_FDRx register.
by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register.
the FIFO Bank 0.
flag RX_DATA_BK1 set in the endpoint’s UDP_CSRx register. An interrupt is pending
for this endpoint while RX_DATA_BK1 is set.
microcontroller’s memory. Data received is available by reading the endpoint’s
UDP_FDRx register.
RX_DATA_BK1 in the endpoint’s UDP_CSRx register.
Bank 0.
1 st Data Payload
2 nd Data Payload
3 rd Data Payload
Microcontroller
Write and Read at the Same Time
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Write
USB Device
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Read
USB Bus
2 nd Data Payload
3 rd Data Payload
1 st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
1768I–ATARM–09-Jul-09
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