AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 677

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

41.9.2
41.10 SPI
41.10.1
41.10.2
41.10.3
41.10.4
1768I–ATARM–09-Jul-09
16-bit write access constraints
Slave Mode Receiver does not mask the highest data bits
No chip select configuration change before end of current transfer
NPCSx rises if no data is to be transmitted
Mode Fault does not allow more than one Master on Chip Select 0
None.
When at least two SMC_CSR registers are programmed as follows:
the associated NCSx signal is not asserted for the write access.
Problem Fix/Workaround
For registers programmed with wait states and 16-bit data bus width configuration, the BAT
fields in these registers must be programmed with the same value.
If the SPI receives a frame followed by 8 bits of data, the user needs to mask the highest byte of
the Receive Holding Register, as this data may be incorrect and not 0.
Problem Fix/Workaround
The user should implement the PDC. If the PDC is not implemented, the user should mask the
highest byte of the Receive Holding register.
If the SPI is programmed in Master Mode and in Fixed Peripheral Mode, and data is being sent
to a slave, the user has to wait for completion of the transfer before changing the slave number.
Programming a new slave number (PCS) and/or a new DLYBCS field locks the SPI on the cur-
rent slave.
Problem Fix/Workaround
The user should use the Variable Peripheral Mode.
If the SPI has sent all the data written in the SPI_TDR, the current NPCS rises immediately. This
might be inconvenient in the case of several SPI peripherals requiring their chip select line to
remain active until a complete data buffer has been transmitted. The PDC channel may be late
in providing data to be transmitted when bus latencies are too high.
Problem Fix/Workaround
For high-speed applications, the relevant PIO pins can be used to manage the data
transmission.
If Mode fault is disabled, Chip Select 0 cannot be driven by a component other than the SPI oth-
erwise the transfer does not occur.
Problem Fix/Workaround
None.
– SMC_SCRx: With wait states (1 < NWS < 127), 16-bit data bus width, and byte write
– SMC_CSRy: With wait states (1 < NWS < 127), 16-bit data bus width, and byte
access (BAT field set to 0)
select access (BAT field set to 1),
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