AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 269

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

23.4.6.2
23.4.6.3
23.4.6.4
1768I–ATARM–09-Jul-09
PLL Source Clock
Divider and Phase Lock Loop Programming
PLLB Divider by 2
The source of PLLs A and B is respectively the output of Divider A, i.e. the Main Clock divided by
DIVA, and the output of Divider B, i.e. the Main Clock divided by DIVB.
As the input frequency of the PLLs is limited, the user has to make sure that the programming of
DIVA and DIVB are compliant with the input frequency range of the PLLs, which is given in the
DC Characteristics section of the product datasheet.
The two dividers increase the accuracy of the PLLA and the PLLB clocks independently of the
input frequency.
The Main Clock can be divided by programming the DIVB field in CKGR_PLLBR and the DIVA
field in CKGR_PLLAR. Each divider can be set between 1 and 255 in steps of 1. When the DIVA
and DIVB fields are set to 0, the output of the divider and the PLL outputs A and B are a contin-
uous signal at level 0. On reset, the DIVA and DIVB fields are set to 0, thus both PLL input
clocks are set to 0.
The two PLLs of the clock generator allow multiplication of the divider’s outputs. The PLLA and
the PLLB clock signals have a frequency that depends on the respective source signal fre-
quency and on the parameters DIV (DIVA, DIVB) and MUL (MULA, MULB). The factor applied to
the source signal frequency is (MUL + 1)/DIV. When MULA or MULB is written to 0, the corre-
sponding PLL is disabled and its power consumption is saved. Re-enabling the PLLA or the
PLLB can be performed by writing a value higher than 0 in the MULA or MULB field,
respectively.
Whenever a PLL is re-enabled or one of its parameters is changed, the LOCKA or LOCKB bit in
PMC_SR is automatically cleared. The values written in the PLLACOUNT or PLLBCOUNT fields
in CKGR_PPLAR and CKGR_PLLBR, respectively, are loaded in the corresponding PLL coun-
ter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0. At this
time, the corresponding LOCK bit is set in PMC_SR and can trigger an interrupt to the proces-
sor. The user has to load the number of Slow Clock cycles required to cover the PLL transient
time into the PLLACOUNT and PLLBCOUNT field. The transient time depends on the PLL fil-
ters. The initial state of the PLL and its target frequency can be calculated using a specific tool
provided by Atmel.
In ARM9-based systems, the PLLB clock may be divided by two. This divider can be enabled by
setting the bit USB_96M of CKGR_PLLBR. In this case, the divider by 2 is enabled and the
PLLB must be programmed to output 96 MHz and not 48 MHz, thus ensuring correct operation
of the USB bus.
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