AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 190

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

18.7.1
Register Name:
Access Type:
Reset Value:
• NWS: Number of Wait States
This field defines the Read and Write signal pulse length from 1 cycle up to 128 cycles.
Note:
Note:
• WSEN: Wait State Enable
0: Wait states are disabled.
1: Wait states are enabled.
• TDF: Data Float Time
The external bus is marked occupied and cannot be used by another chip select during TDF cycles. Up to 15 cycles can be
defined and represents the time allowed for the data output to go to high impedance after the memory is disabled.
• BAT: Byte Access Type
This field is used only if DBW defines a 16-bit data bus.
0: Chip select line is connected to two 8-bit wide devices.
1: Chip select line is connected to a 16-bit wide device.
190
Number of Wait States
WSEN
DRP
31
23
15
–
–
7
When WSEN i 0, NWS will be read to 0 whichever the previous programmed value should be.
1. Assuming WSEN Field = 0.
X + 1
AT91RM9200
SMC Chip Select Registers
0
1
2
(1)
30
22
14
SMC_CSR0..SMC_CSR7
Read-write
See
–
6
Table 18-4 on page 189
DBW
Up to X = 127
NWS Field
Don’t Care
RWHOLD
0
1
29
21
13
–
5
Standard Read Protocol
BAT
NRD Pulse Length
28
20
12
–
4
X + 1+ ½ cycles
1 + ½ cycles
2 + ½ cycles
½ cycle
NWS
27
19
11
–
–
3
Early Read Protocol
NRD Pulse Length
X + 2 cycles
2 cycles
3 cycles
1 cycle
26
18
10
–
2
TDF
RWSETUP
25
17
9
1
NWR Pulse Length
ACSS
1768I–ATARM–09-Jul-09
X + 1 cycle
2 cycles
½ cycle
1 cycle
24
16
8
0