AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 67

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

12.6.4.3
12.6.5
12.6.5.1
1768I–ATARM–09-Jul-09
IEEE 1149.1 JTAG Boundary Scan
Application Board Restriction
JTAG Boundary Scan Register
The TCLK signal needs to be set with care, some timing parameters are required.
Refer to AT91RM9200
The specified target system connector is the AMP Mictor connector.
The connector must be oriented on the application board as described below in
view of the PCB is shown from above with the trace connector mounted near the edge of the
board. This allows the Trace Port Analyzer to minimize the physical intrusiveness of the inter-
connected target.
Figure 12-6. AMP Mictor Connector Orientation
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging
technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST
and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-
formed (NRST and NTRST) after JTAGSEL is changed.
Two Boundary Scan Descriptor Language (BSDL) files are provided to set up testing. Each
BSDL file is dedicated to a specific packaging.
The Boundary Scan Register (BSR) contains 449 bits which correspond to active pins and asso-
ciated control signals.
Each AT91RM9200 input pin has a corresponding bit in the Boundary Scan Register for
observability.
Each AT91RM9200 output pin has a corresponding 2-bit register in the BSR. The OUTPUT bit
contains data which can be forced on the pad. The CTRL bit can put the pad into high
impedance.
“JTAG/ICE Timings” on page 657
38 37
2
1
AT91RM9200-based
Application Board
Pin 1Chamfer
and
“ETM Timings” on page
AT91RM9200
Figure
660.
12-6. The
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