AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 215

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

20. Burst Flash Controller (BFC)
20.1
1768I–ATARM–09-Jul-09
Overview
The Burst Flash Controller (BFC) provides an interface for external 16-bit Burst Flash devices
and handles an address space of 256M bytes. It supports byte, half-word and word aligned
accesses and can access up to 32M bytes of Burst Flash devices. The BFC also supports data
bus and address bus multiplexing. The Burst Flash interface supports only continuous burst
reads. Programmable burst lengths of four or eight words are not possible. The BFC never gen-
erates an abort signal, regardless of the requested address within the 256M bytes of address
space.
The BFC can operate with two burst read protocols depending on whether or not the address
increment of the Burst Flash device is signal controlled. The Burst Flash Controller Mode Regis-
ter (BFC_MR) located in the BFC user interface is used in programming Asynchronous or Burst
Operating Modes. In Burst Mode, the read protocol, Clock Controlled Address Advance, auto-
matically increments the address at each clock cycle. Whereas in Signal Controlled Address
Advance protocol the address is incremented only when the Burst Address Advance signal is
active. When Address and Data Bus Multiplexing Mode is chosen, the sixteen lowest address
bits are multiplexed with the data bus.
The BFC clock speed is programmable to be either master clock or master clock divided by 2 or
4. Page size handling (16 bytes to 1024 bytes) is required by some Burst Flash devices unable
to handle continuous burst read. The number of latency cycles after address valid goes up to
sixteen cycles. The number of latency cycles after output enable runs between one and three
cycles. The Burst Flash Controller can also be programmed to suspend and maintain the current
burst. This attribute gives other devices the possibility to share the BFC busses without any loss
of efficiency. In Burst Mode, the BFC can restart a sequential access without any additional
latency.
Features of the Burst Flash Controller are:
• Multiple Access Modes Supported
• Adaptability to Different Device Speed Grades
• Adaptability to Different Device Access Protocols and Bus Interfaces
– Asynchronous or Burst Mode Byte, Half-word or Word Read Accesses
– Asynchronous Mode Half-word Write Accesses
– Programmable Burst Flash Clock Rate
– Programmable Data Access Time
– Programmable Latency after Output Enable
– Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled
– Multiplexed or Separate Address and Data Busses
– Continuous Burst and Page Mode Accesses Supported
Address Advance
AT91RM9200
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