AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 94

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

13.5
94
Hardware and Software Constraints
AT91RM9200
The software limitations of the Boot Program are:
The hardware limitations of the Boot Program are:
The SPI and TWI drivers use several PIOs in alternate functions to communicate with devices.
Care must be taken when these PIOs are used by the application. The devices connected could
be unintentionally driven at boot time, and electrical conflicts between SPI or TWI output pins
and the connected devices may appear.
To assure correct functionality, it is recommended to plug in critical devices to other pins or to
boot on an external 16-bit parallel memory by setting bit BMS.
Table 13-4
are driven during the boot sequence for a period of about 6 ms if no correct boot program is
found. The download through the TWI takes about 5 sec for 64K bytes due to the TWI bit rate
(100 Kbits/s).
For the DataFlash driven by SPCK signal at 12 MHz, the time to download 64K bytes is reduced
to 66 ms.
Before performing the jump to the application in internal SRAM, all the PIOs and peripherals
used in the Boot Program are set to their reset state.
Table 13-4.
Note:
Pin Used
MOSI
SPCK
NPCS0
TWD
TWCK
• The downloaded code size is less than the SRAM size -4K embedded in the product.
• The device address of the EEPROM must be 0 on the TWI bus.
• The code is always downloaded from the device address 0x0000_0000 (DataFlash,
• The downloaded code must be position-independent or linked at address 0x0000_0000.
• The DataFlash must be connected to NPCS0 of the SPI.
• The 8-bit parallel Flash must be connected to NCS0 of the EBI.
• The Boot Program initializes the DBGU pins multiplexed on the PIO common to both the 208-
• Using an external clock source on the XIN pin is not possible as the main oscillator is enabled
EEPROM) to the address 0x0000_0000 of the internal SRAM (after remap).
lead PQFP and 256-ball BGA packages, in this case meaning PIOA.
by the Boot ROM.
(1)
(1)
(1)
(1)
(1)
1. See
contains a list of pins that are driven during the Boot Program execution. These pins
Pins Driven during Boot Program Execution
Section 10.3 “Peripheral Multiplexing on PIO Lines” on page
SPI (DataFlash)
O
O
O
X
X
22.
TWI (EEPROM)
I/O
O
X
X
X
1768I–ATARM–09-Jul-09