ADUC7032BSTZ-8V-RL Analog Devices Inc, ADUC7032BSTZ-8V-RL Datasheet - Page 104

• Manufacturer Part Number: ADUC7032BSTZ-8V-RL
• Description: IC BATTERY SENSOR PREC 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8V-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: ADUC7032BSTZ-8V-RLCT

Preliminary Technical Data
WAKE-UP(WU)
The Wake Up pin is a high voltage GPIO controlled via HVCON and HVDAT.
Wake-Up(WU) Pin Circuit Description
The WU pin is configured by default as an output with an
internal 10KΩ pull-down resistor and high side FET driver. The
WU pin in its default mode of operation is specified to generate
an active high system wake-up request by forcing the external
system WU bus high. User code can assert the WU output by
writing directly to HVCFG0[4].
The internal FET is capable of sourcing significant current and
therefore a substantial on-chip self-heating can occur if this
driver is asserted for a long time period. For this reason a
Monoflop, a 1.3 second timeout timer, has been included. By
default the Monoflop is enabled and will disable the Wake
Driver after 1.3 seconds. It is possible to disable the Monoflop
via HVCFG1[1]. If the Wake Monoflop is disabled, then the
Wake driver should be disabled after 1.3s.
The Wake Pin also features a short circuit detection feature.
When the wake Pin sources more than 200mA for 400uS a high
voltage interrupt will be generated with HVMON[0] set.
OUTPUT CONTROL
SHORT CIRCUIT
PROTECTION
HVCFG0[4]
HVMON[0]
HVMON[7]
NORMAL
NORMAL
IMMUNITY
GLITCH
400µs
READ-BACK
HVCFG1[4]
ENABLE
SHORT CIRCUIT
TRIP REFERENCE
Figure 36 : WU Circuit, Block Diagram
3V
Rev. PrD | Page 104 of 128
6.6kΩ
3.3kΩ
IO_VSS
R1
R2
VDD
INTERNAL
SENSE
RESISTOR
6kΩ
INTERNAL
10kΩ
RESISTOR
It should be noted the output will only respond after the
10usecs latency through the (serial communication based) high
voltage interface
By Default, a thermal shutdown event disables the Wake
Driver. The Wake driver must be re-enabled manually after a
thermal event via HVCFG1[3]. It is possible to disable the
automatic shutdown during a thermal event via HVCFG0[7].
The WU pin can be configured in I/O mode by writing a 1 to
HVCFG1[4]. In this mode, a rising or falling edge will
immediately generate a high voltage interrupt. HVMON[7]
directly reflects the state of the external WU pin. This
comparator has a trip level of 3V
O/C
DIAGNOSTIC
RESISTOR
HVCFG1[0]
EXTERNAL
WU PIN
CURRENT-LIMIT
EXTERNAL
RESISTOR
39Ω
TYP
C
91nF
.
LOAD
R
1kΩ
LOAD
ADuC7032
EXTERNAL
WAKE BUS