ADUC7032BSTZ-8V-RL Analog Devices Inc, ADUC7032BSTZ-8V-RL Datasheet - Page 71

• Manufacturer Part Number: ADUC7032BSTZ-8V-RL
• Description: IC BATTERY SENSOR PREC 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8V-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: ADUC7032BSTZ-8V-RLCT

Preliminary Technical Data
POWCON Register :
Name :
Address :
Default Value :
Access :
Function :
1
2
3
4
5
Bit
31-8
7
6
5
4
3
2-0
Timer peripherals will be powered down if driven from the PLL Output clock. Timers driven from an active clock source will stay in normal power mode.
The peripherals that are powered down by this bit are as follows:
LIN can still respond to wake-up events even if this bit is cleared.
Wake-Up Timer (Timer2) can still be active if driven from low power oscillator even if this bit is set.
If user code powers down the MCU, a dummy MCU cycle should be included after the power-down command is written to POWCON.
SRAM, Flash/EE Memory and GPIO Interfaces
SPI and UART Serial Ports
Description
Reserved
Precision 131kHz Input Enable:
Cleared by the user to Power down the Precision 131kHz Input Enable.
Set by the user to enable the Precision 131kHz Input Enable. The Precision 131kHz oscillator must also be enabled via
HVCFG0[6]. Setting this bit increases current consumption by approximately 50uA and should be disabled when not in use.
XTAL Power Down:
Cleared by the user to Power down the external crystal circuitry.
Set by the user to enable the external crystal circuitry.
PLL Power Down
This bit is cleared to 0 to power down the PLL. The PLL can not be powered down if either the core or peripherals are enabled:
Bits 3, 4 and 5 must be cleared simultaneously.
Set by default, and set by hardware on a wake up event
Peripherals
Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled: bits 3 and 4 must be
cleared simultaneously.
Set by default, or and by hardware on a wake up event
Core Power Down:
Cleared to power down the ARM Core
Set by default, and set by hardware on a wake up event
CD Core clock divider bits:
000
001
010
011
100
101
110
111
POWCON
0xFFFF0408
0x079
Read/Write
This 8-bit register allows user code dynamically enter various Low Power modes and modify the CD divider which
controls the speed of the ARM7TDMI Core.
2,3, 4
Power Down:
1
:
5
20.48 MHz
10.24 MHz
5.12 MHz
2.56 MHz
1.28 MHz
640 kHz
320 kHz
160 kHz
Table 37 : POWCON MMR bit designations
Rev. PrD | Page 71 of 128
48.83ns
97.66ns
195.31ns
390.63ns
781.25ns
1.56µs
3.125µs
6.25µs
ADuC7032