ADUC7032BSTZ-8V-RL Analog Devices Inc, ADUC7032BSTZ-8V-RL Datasheet - Page 30

• Manufacturer Part Number: ADUC7032BSTZ-8V-RL
• Description: IC BATTERY SENSOR PREC 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8V-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: ADUC7032BSTZ-8V-RLCT

Preliminary Technical Data
ADUC7032 RESET
There are four kinds of reset: external reset, Power-on-reset,
watchdog reset and software reset. The RSTSTA register
indicates the source of the last reset and can also be written by
user code to initiate a software reset event. The bits in this
register can be cleared to ‘0’ by writing to the RSTCLR MMR at
Note1: If LVF is enabled(HVCFG0[2]), RAM has not been corrupt by the POR reset mechanism if LVF Status bit HVSTA[6] is ‘1’.
RSTCLR Register :
Name :
Address :
Default Value :
Access :
Function :
Bit
7-4
3
2
1
0
RESET
POR
Watchdog
Reset
Software Reset
External Reset
Pin
Description
Not Used
These bits are not used and will always read as ‘0’
External Reset
Set to 1 automatically when an external reset occurs
Cleared by setting the corresponding bit in RSTCLR
Software Reset
Set to ‘1’ by user code to generate a software reset.
Cleared by setting the corresponding bit in RSTCLR
Watchdog timeout
Set to 1 automatically when a watchdog timeout occurs
Cleared by setting the corresponding bit in RSTCLR
Power-on-reset
Set automatically when a power-on-reset occurs
Cleared by setting the corresponding bit in RSTCLR
IMPACT
RSTCLR
0xFFFF0234
0x00
Write Only
This 8-bit write only register clears the
corresponding bit in RSTSTA.
Reset
External
Pins to
Default
State
Kernel
Executed
Table 10: RSTSTA/RSTCLR MMR Bit Designations
Reset All
External MMRs
(excluding
RSTSTA)
Table 9 : Device RESET Implications
Rev. PrD | Page 30 of 128
0xFFFF0234. The bit designations in RSTCLR mirror those of
RSTSTA. These registers can be used during a reset exception
service routine to identify the source of the reset. The
implications of all four kinds of reset event are tabulated in
Table 9 below.
RSTSTA Register :
Name :
Address :
Default Value :
Access :
Function :
Reset All
HV
Indirect
Registers
Peripherals
Reset
RSTSTA
0xFFFF0230
0x01
Read/Write Access
This 8-bit register indicates the source of
the last reset event and can also be written
by user code to initiate a software reset.
RAM
Valid
Note 1
RSTSTA
(Status after
Reset Event)
RSTSTA[0] =1
RSTSTA[1] =1
RSTSTA[2] =1
RSTSTA[3] =1
ADuC7032