ADUC7032BSTZ-8V-RL Analog Devices Inc, ADUC7032BSTZ-8V-RL Datasheet - Page 96
![IC BATTERY SENSOR PREC 48-LQFP](/photos/6/59/65923/505-48-lqfp_sml.jpg)
ADUC7032BSTZ-8V-RL
Manufacturer Part Number
ADUC7032BSTZ-8V-RL
Description
IC BATTERY SENSOR PREC 48-LQFP
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.ADUC7032BSTZ-8V-RL.pdf
(128 pages)
Specifications of ADUC7032BSTZ-8V-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
POR, PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
ADUC7032BSTZ-8V-RLCT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADUC7032BSTZ-8V-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Preliminary Technical Data
GPIO Port2 Clear Register :
Name :
Address :
Default Value :
Access :
Function :
Bit
31-23
22
21
20-18
17
16
15-0
Description
Reserved
These bits are reserved and should be written as 0 by user code
Port 2.6 Clear Bit
This bit is set to 1 by user code to clear the external GPIO13 pin low.
If user software clears this bit to 0, this will have no effect on the external GPIO8 pin.
Port 2.5 Clear Bit
This bit is set to 1 by user code to clear the external GPIO12 pin low.
If user software clears this bit to 0, this will have no effect on the external GPIO7 pin.
Reserved
These bits are reserved and should be written as 0 by user code
Port 2.1 Clear Bit
This bit is set to 1 by user code to clear the external GPIO8 pin low.
If user software clears this bit to 0, this will have no effect on the external GPIO8 pin.
Port 2.0 Clear Bit
This bit is set to 1 by user code to clear the external GPIO7 pin low.
If user software clears this bit to 0, this will have no effect on the external GPIO7 pin.
Reserved
These bits are reserved and should be written as 0 by user code
GP2CLR
0xFFFF0D48
0x00000000
Read/Write
This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low only.
User code can do this via the GP2CLR MMR without having to modify or maintain the status of any other GPIO
pins as user code would need to do when using GP2DAT.
Table 60 : GP2CLR MMR Bit Descriptions
Rev. PrD | Page 96 of 128
ADuC7032