ADUC7032BSTZ-8V-RL Analog Devices Inc, ADUC7032BSTZ-8V-RL Datasheet - Page 63

• Manufacturer Part Number: ADUC7032BSTZ-8V-RL
• Description: IC BATTERY SENSOR PREC 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8V-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: ADUC7032BSTZ-8V-RLCT

Preliminary Technical Data
Figure 23 Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x961F)
Changing SF to 0x1D and setting AF to 0x3F, again with the
Chop bit enabled, configures the ADC into its minimum
through-put rate in Normal Mode of 4Hz. The digital filter
frequency response with this configuration is shown below in
Figure 24.
Figure 24 : Typical Digital Filter Response at FADC=4Hz, (ADCFLT = 0xBF1D)
In ADC Low Power Mode, the ADC, Sigma-Delta modulator
clock no longer driven at 512KHz but is driven directly from
the on-chip low power (131KHz) oscillator. Subsequently, for
the same ADCFLT configurations in Normal Mode, all filter
values should be scaled by a factor of approximately 4. This
means that is possible to configure the ADC for 1Hz through-
put is Low Power Mode. The filter frequency response for this
configuration is shown below in Figure 25.
[dB]
[dB]
H(f)
H(f)
-100
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
0
0
0
20
40
60
20
80
100
120
40
140
160
180
Rev. PrD | Page 63 of 128
200
60
f
f
Mode
Normal
Normal
Normal
Normal
Normal
Normal
Power
Power
Power
ADC
Low
Low
Low
Figure 25 : Typical Digital Filter Response at FADC=1Hz, (ADCFLT = 0xBD1F
In general, it should be noted that it is possible to program
different values of SF and AF in the ADCFLT register and
achieve the same ADC update rate. In practical terms the trade-
off with any value of ADCFLT will be frequency response
versus ADC noise. For optimum filter response and ADC noise
when using combinations of SF and AF, a good rule of thumb
to use would be to first choose an SF in the range of 16 – 40
(dec) or 0x10 to 0x28 and then increase the AF value to
achieve the required ADC through-put. Table 32 shows some
common ADCFLT configurations.
[dB]
H(f)
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
0
0x1D
0x1F
0x07
0x07
0x03
0x00
0x10
0x10
0x1F
SF
2
Table 32 : Common ADCFLT Configurations
4
0x3D
0x3F
0x16
0x00
0x00
0x00
0x01
0x03
0x09
AF
6
Chop On
Chop On
Chop On
Chop On
Chop On
Config
Running
Average
Running
Average
Modifiy
Other
Sinc 3
None
8
10
ADCFLT
0xBF1D
0xBD1F
0x0007
0x0087
0x4003
0x4000
0x8310
0x8910
0x961F
12
14
ADuC7032
16
10Hz
1KHz
1KHz
2KHz
8KHz
20Hz
10Hz
F
4Hz
1Hz
ADC
18
0.5secs
0.2secs
3msecs
T
3msec
2msec
100ms
200ms
0.5ms
2sec
SETTLE
20
f