MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 228

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

External Interface Module (EIM)
Basic operation of the bus is a three-clock bus cycle:
13.4.2
The data transfer operation is controlled by an on-chip state machine. Each bus clock cycle is divided into
two states. Even states occur when CLKOUT is high and odd states occur when CLKOUT is low. The state
transition diagram for basic and fast termination read and write cycles are shown in
13-4
1. During the first clock, the address, attributes, and TS are driven.
2. Data and TA are sampled during the second clock of a bus-read cycle. During a read, the external
3. The last clock of the bus cycle uses what would be an idle clock between cycles to provide hold
device provides data and is sampled at the rising edge at the end of the second bus clock. This data
is concurrent with TA, which is also sampled at the rising edge of the clock.
During a write, the ColdFire device drives data from the rising clock edge at the end of the first
clock to the rising clock edge at the end of the bus cycle. Wait states can be added between the first
and second clocks by delaying the assertion of TA. TA can be configured to be generated internally
through the CSCRs. If TA is not generated internally, the system must provide it externally.
time for address, attributes and write data.
write operations.
0
1
Multiple
0
1
Multiple
0
1
Multiple
Data Transfer Cycle States
Number of CSCR Matches
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 13-2. Accesses by Matches in CSCRs and DACRs
0
1
Multiple
0
0
1
1
Multiple
Multiple
Number of DACR Matches
Figure 13-6
and
External
Defined by CSCR
External, burst-inhibited, 32-bit
Defined by DACRs
Undefined
Undefined
Undefined
Undefined
Undefined
Figure 13-8
Type of Access
show the basic read and
Freescale Semiconductor
Figure
13-4.