MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 456

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

I
24.1.2
I
minimizing the interconnection between devices. This bus is suitable for applications that require
occasional communication between many devices over a short distance. The flexible I
additional devices to connect to the bus for expansion and system development.
The interface operates up to 100 Kbps with maximum bus loading and timing. The device is capable of
operating at higher baud rates, up to a maximum of the internal bus clock divided by 20, with reduced bus
loading. The maximum communication length and the number of devices connected are limited by a
maximum bus capacitance of 400 pF.
The I
corruption in the event that multiple devices attempt to control the bus simultaneously. This feature
supports complex applications with multiprocessor control and can be used for rapid testing and alignment
of end products through external connections to an assembly-line computer.
24.1.3
The I
24-2
2
2
C Interface
C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,
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2
2
C system is a true multiple-master bus; it uses arbitration and collision detection to prevent data
C module has these key features:
Compatibility with I
Multiple-master operation
Software-programmable for one of 50 different serial clock frequencies
Software-selectable acknowledge bit
Interrupt-driven, byte-by-byte data transfer
Arbitration-lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
START and STOP signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus-busy detection
Overview
Features
The I
information on system configuration, protocol, and restrictions, see The I
Bus Specification, Version 2.1.
The GPIO module must be configured to enable the peripheral function of
the appropriate pins (refer to
prior to configuring the I
2
C module is compatible with the Philips I
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
2
C bus standard version 2.1
2
C module.
Chapter 26, “General Purpose I/O
NOTE
NOTE
2
C bus protocol. For
Module”)
Freescale Semiconductor
2
2
C bus allows
C