MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 47

IC MPU 32BIT COLDF 256-MAPBGA

MCF5214CVF66

Manufacturer Part Number
MCF5214CVF66
Description
IC MPU 32BIT COLDF 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet

Specifications of MCF5214CVF66

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Package
256MA-BGA
Device Core
ColdFire
Family Name
MCF521x
Maximum Speed
66 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
142
Interface Type
QSPI/UART/I2C/CAN
On-chip Adc
8-chx10-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Part Number:
MCF5214CVF66
Manufacturer:
Freescale Semiconductor
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Chapter 2
ColdFire Core
2.1
This section describes the organization of the Version 2 (V2) ColdFire
of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the
ColdFire Family Programmer’s Reference Manual.
2.1.1
As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines decoupled by an
instruction buffer.
The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched
instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the
Freescale Semiconductor
Introduction
Overview
Instruction
Execution
Operand
Pipeline
Pipeline
Fetch
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
DSOC
AGEX
IAG
IC
IB
Decode & Select,
Figure 2-1. V2 ColdFire Core Pipelines
Instruction Buffer
Operand Fetch
Generation,
Fetch Cycle
Instruction
Generation
Instruction
Address
Address
Execute
FIFO
®
processor core and an overview
Address [
Read Data[31:0]
Write Data[31:0]
31
:0]
2-1

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