MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 527

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

26.4
26.4.1
The initial pin function is determined during reset configuration. The pin assignment registers allow the
user to select between digital I/O or another pin function after reset.
In single-chip mode, all pins are configured as digital I/O by default, except for debug data pins
(DDATA[3:0]) and processor status pins (PST[3:0]). These pins are configured for their primary functions
by default in all modes.
Every digital I/O pin is individually configurable as an input or an output via a data direction register
(DDRn).
Every port has an output data register (PORTn) and a pin data register (PORTnP/SETn) to monitor and
control the state of its pins. Data written to a PORTn register is stored and then driven to the corresponding
port n pins configured as outputs.
Reading a PORTn register returns the current state of the register regardless of the state of the
corresponding pins.
Reading a PORTnP/PSETn register returns the current state of the corresponding pins when configured as
digital I/O, regardless of whether the pins are inputs or outputs.
Every port has a PORTnP/SETn register and a clear register (CLRn) for setting or clearing individual bits
in the PORTn register.
In master mode, port A and B function as the upper external data bus, D[31:16]. When the PCDPA bit is
set, ports C and D function as the lower external data bus, D[15:0]. Ports E–J are configured to support
external memory functions.
The ports module does not generate interrupt requests.
26.4.2
Input data on all pins configured as digital I/O is synchronized to the rising edge of CLKOUT, as shown
in
Freescale Semiconductor
Figure
Bits
2
1
0
26-30.
Functional Description
Overview
Port Digital I/O Timing
PUAPA2
PUAPA1
PUAPA0
Name
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Port UA pin assignment 2. This bit configures the port UA2 pin for its primary function
(UTXD1) or digital I/O.
1 Port UA2 pin configured for primary function (UTXD1)
0 Port UA2 pin configured for digital I/O
Port UA pin assignment 1. This bit configures the port UA1 pin for its primary function
(URXD0) or digital I/O.
1 Port UA1 pin configured for primary function (URXD0)
0 Port UA1 pin configured for digital I/O
Port UA pin assignment 0. This bit configures the port UA0 pin for its primary function
(UTXD0) or digital I/O.
1 Port UA0 pin configured for primary function (UTXD0)
0 Port UA0 pin configured for digital I/O
Table 26-19. PUAPAR Field Descriptions (continued)
Description
General Purpose I/O Module
26-27