MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 33

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Chapter 1
Overview
This chapter provides an overview of the microprocessor features, including the major functional
components.
1.1
A block diagram of the MCF528x and MCF521x is shown in
Freescale Semiconductor
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Static Version 2 ColdFire variable-length RISC processor
— Static operation
— On-chip 32-bit address and data path
— Processor core and bus frequency up to 80 MHz
— Sixteen general-purpose 32-bit data and address registers
— ColdFire ISA_A with extensions to support the user stack pointer register, and four new
— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit
— Illegal instruction decode that allows for 68K emulation support
System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with one user-visible hardware breakpoint register (PC and address
On-chip memories
— 2-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters
— 512 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
Power management
— Fully-static operation with processor sleep and whole chip stop modes
— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
Fast Ethernet Controller (FEC) (not available on the MCF5214 and MCF5216)
— 10BaseT capability, half- or full-duplex
— 100BaseT capability, half- or limited-throughput full-duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
Key Features
instructions for improved bit processing
signal processing algorithms
with optional data) that can be configured into a 1- or 2-level trigger
(e.g., DMA, FEC) with standby power supply support
(256 Kbytes on the MCF5281 and MCF5214, no Flash on MCF5280)
– This product incorporates SuperFlash® technology licensed from SST.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure
1-1. The main features are as follows:
1-1