MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 295

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.3.5
When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is read on
A[10:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding processor address pins
must be determined while being aware of masking requirements.
Table 15-30
Next, this information is mapped to an address to determine the hexadecimal value.
Although A[31:20] corresponds to the address programmed in DACR0, according to how DACR0 and
DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before the mode register bit is set,
DMR0[19] must be set to enable masking.
15.3.6
The following assembly code initializes the SDRAM example.
Freescale Semiconductor
Setting
Setting
(hex)
(hex)
Field
Field
Mode Register Initialization
Initialization Code
lists the desired initialization setting:
31
15
30
14
Processor Pins
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
29
13
A20
A19
A18
A17
A10
A11
A12
A13
A14
A15
A9
Table 15-31. Mode Register Mapping to A[31:0]
28
12
Table 15-30. Mode Register Initialization
27
11
SDRAM Pins
26
10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0000_100x_xxxx_xxxx
25
xxxx_xxxx_xxxx_000x
9
24
8
0000
0800
Mode Register Initialization
Reserved
Opmode
Opmode
CASL
CASL
CASL
23
7
WB
BT
BL
BL
BL
22
6
21
5
Synchronous DRAM Controller Module
20
4
X
0
0
0
0
0
1
0
0
0
0
19
3
18
2
17
1
16
V
0
15-23