S912XEQ384J3CAL Freescale Semiconductor, S912XEQ384J3CAL Datasheet - Page 1096

• Manufacturer Part Number: S912XEQ384J3CAL
• Description: IC MCU 16BIT 384KB FLASH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEQ384J3CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 24 KB
• Interface Type: SCI, SPI, I2C, CAN
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 3.13 V to 5.5 V
• Maximum Operating Temperature: + 260 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 28 768 KByte Flash Module (S12XFTM768K4V2)
28.3.2.6
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
All assigned bits in the FERCNFG register are readable and writable.
1096
PGMERIE
EPVIOLIE
ERSERIE
Offset Module Base + 0x0005
Reset
FDFD
FSFD
Field
Field
1
0
7
6
4
W
R
ERSERIE
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The
FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual
double bit fault is detected.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Force Single Bit Fault Detect
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The
FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single
bit fault is detected.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see
EEE Erase Error Interrupt Enable — The ERSERIE bit controls interrupt generation when a failure is detected
during an EEE erase operation.
0 ERSERIF interrupt disabled
1 An interrupt will be requested whenever the ERSERIF flag is set (see
EEE Program Error Interrupt Enable — The PGMERIE bit controls interrupt generation when a failure is
detected during an EEE program operation.
0 PGMERIF interrupt disabled
1 An interrupt will be requested whenever the PGMERIF flag is set (see
EEE Protection Violation Interrupt Enable — The EPVIOLIE bit controls interrupt generation when a
protection violation is detected during a write to the buffer RAM EEE partition.
0 EPVIOLIF interrupt disabled
1 An interrupt will be requested whenever the EPVIOLIF flag is set (see
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
Flash Error Configuration Register (FERCNFG)
0
7
Section
register is set (see
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section
= Unimplemented or Reserved
28.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
28.3.2.6)
PGMERIE
Figure 28-10. Flash Error Configuration Register (FERCNFG)
0
6
Table 28-15. FCNFG Field Descriptions (continued)
Section
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 28-16. FERCNFG Field Descriptions
28.3.2.6)
0
0
5
—
The FSFD bit allows the user to simulate a single bit fault during Flash array
EPVIOLIE
0
4
Description
Description
ERSVIE1
0
3
ERSVIE0
Section
Section
Section
0
2
28.3.2.8)
28.3.2.8)
28.3.2.8)
Freescale Semiconductor
DFDIE
0
1
Section
SFDIE
28.3.2.7)
0
0