S912XEQ384J3CAL Freescale Semiconductor, S912XEQ384J3CAL Datasheet - Page 262

IC MCU 16BIT 384KB FLASH 112LQFP

S912XEQ384J3CAL

Manufacturer Part Number
S912XEQ384J3CAL
Description
IC MCU 16BIT 384KB FLASH 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S912XEQ384J3CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Core
HCS12X
Data Bus Width
16 bit
Data Ram Size
24 KB
Interface Type
SCI, SPI, I2C, CAN
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
1
Operating Supply Voltage
3.13 V to 5.5 V
Maximum Operating Temperature
+ 260 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XEQ384J3CAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 5 External Bus Interface (S12XEBIV4)
state operation (stretching) of the external bus access is done in emulation modes when accessing internal
memory or emulation memory addresses.
In both modes observation of the internal operation is supported through the external bus (internal
visibility).
5.5.2.1
This mode is used for emulation systems in which the target application is operating in normal single-chip
mode.
Figure 5-5
The timing diagram for this operation is shown in:
The associated timing numbers are given in:
Timing considerations:
262
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Figure ‘Example 2a: Emulation Single-Chip Mode — Read Followed by Write’
Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAIT disabled)’
Signals muxed with address lines ADDRx, i.e., IVDx, IQSTATx and ACCx, have the same timing.
LSTRB has the same timing as RW.
shows the PRU connection with the available external bus signals in an emulator application.
Example 2a: Emulation Single-Chip Mode
ADDR[22:20]/ACC[2:0]
Figure 5-5. Application in Emulation Single-Chip Mode
ADDR[22:0]/IVD[15:0]
S12X_EBI
MC9S12XE-Family Reference Manual , Rev. 1.23
ADDR[19:16]/
IQSTAT[3:0]
DATA[15:0]
ECLKX2
LSTRB
ECLK
RW
EMULMEM
PRU
Emulator
PRR
Ports
Freescale Semiconductor

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