S912XEQ384J3CAL Freescale Semiconductor, S912XEQ384J3CAL Datasheet - Page 629

IC MCU 16BIT 384KB FLASH 112LQFP

S912XEQ384J3CAL

Manufacturer Part Number
S912XEQ384J3CAL
Description
IC MCU 16BIT 384KB FLASH 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S912XEQ384J3CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Core
HCS12X
Data Bus Width
16 bit
Data Ram Size
24 KB
Interface Type
SCI, SPI, I2C, CAN
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
1
Operating Supply Voltage
3.13 V to 5.5 V
Maximum Operating Temperature
+ 260 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XEQ384J3CAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
16.3.2.16 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
Module Base + 0x000E
Module Base + 0x000F
Write: Unimplemented
Write: Unimplemented
Reset:
Reset:
W
W
R
R
RXERR7
TXERR7
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
0
0
7
7
Figure 16-19. MSCAN Transmit Error Counter (CANTXERR)
Figure 16-18. MSCAN Receive Error Counter (CANRXERR)
RXERR6
TXERR6
= Unimplemented
= Unimplemented
6
0
6
0
MC9S12XE-Family Reference Manual Rev. 1.23
RXERR5
TXERR5
0
0
5
5
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
RXERR4
TXERR4
NOTE
NOTE
4
0
4
0
RXERR3
TXERR3
0
0
3
3
RXERR2
TXERR2
2
0
2
0
Access: User read/write
Access: User read/write
RXERR1
TXERR1
0
0
1
1
RXERR0
TXERR0
0
0
0
0
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