S912XEQ384J3CAL Freescale Semiconductor, S912XEQ384J3CAL Datasheet - Page 532

• Manufacturer Part Number: S912XEQ384J3CAL
• Description: IC MCU 16BIT 384KB FLASH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEQ384J3CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 24 KB
• Interface Type: SCI, SPI, I2C, CAN
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 3.13 V to 5.5 V
• Maximum Operating Temperature: + 260 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.2.3
This pin serves as input capture or output compare for channel 5.
14.2.4
This pin serves as input capture or output compare for channel 4.
14.2.5
This pin serves as input capture or output compare for channel 3.
14.2.6
This pin serves as input capture or output compare for channel 2.
14.2.7
This pin serves as input capture or output compare for channel 1.
14.2.8
This pin serves as input capture or output compare for channel 0.
14.3
This section provides a detailed description of all memory and registers.
14.3.1
The memory map for the ECT module is given below in the
is the address offset. The total address for each register is the sum of the base address for the ECT module
and the address offset for each register.
14.3.2
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
532
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Memory Map and Register Definition
IOC5 — Input Capture and Output Compare Channel 5
IOC4 — Input Capture and Output Compare Channel 4
IOC3 — Input Capture and Output Compare Channel 3
IOC2 — Input Capture and Output Compare Channel 2
IOC1 — Input Capture and Output Compare Channel 1
IOC0 — Input Capture and Output Compare Channel 0
Module Memory Map
Register Descriptions
For the description of interrupts see
MC9S12XE-Family Reference Manual Rev. 1.23
NOTE
Section 14.4.3, “Interrupts”.
Table
14-2. The address listed for each register
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