S912XEQ384J3CAL Freescale Semiconductor, S912XEQ384J3CAL Datasheet - Page 259

• Manufacturer Part Number: S912XEQ384J3CAL
• Description: IC MCU 16BIT 384KB FLASH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEQ384J3CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 24 KB
• Interface Type: SCI, SPI, I2C, CAN
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 3.13 V to 5.5 V
• Maximum Operating Temperature: + 260 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that
are able to produce LSTRB = ADDR0 = 1. This is summarized in
Freescale Semiconductor
Word write of data on DATA[15:0] at an even and even+1
address
Byte write of data on DATA[7:0] at an odd address
Byte write of data on DATA[15:8] at an even address
Word write at an odd and odd+1 internal RAM address
(misaligned — only in emulation modes)
Word read of data on DATA[15:0] at an even and even+1
address
Byte read of data on DATA[7:0] at an odd address
Byte read of data on DATA[15:8] at an even address
Word read at an odd and odd+1 internal RAM address
(misaligned - only in emulation modes)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Table 5-20. Access in Emulation Modes and Special Test Mode
Access
MC9S12XE-Family Reference Manual Rev. 1.23
RW LSTRB ADDR0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Table
0
1
0
1
0
1
0
1
Chapter 5 External Bus Interface (S12XEBIV4)
Out
Out
Out data(odd+1) Out
I/O
5-20.
In
In
In
In
In
DATA[15:8]
data(odd+1)
data(addr)
data(even)
data(even)
data(even)
data(odd)
x
x
Out
Out
I/O
In
In
In
In
In
DATA[7:0]
data(even+1)
data(addr)
data(odd)
data(odd)
data(odd)
data(odd)
data(odd)
x
x
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