S912XEQ384J3CAL Freescale Semiconductor, S912XEQ384J3CAL Datasheet - Page 239

• Manufacturer Part Number: S912XEQ384J3CAL
• Description: IC MCU 16BIT 384KB FLASH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEQ384J3CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 24 KB
• Interface Type: SCI, SPI, I2C, CAN
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 3.13 V to 5.5 V
• Maximum Operating Temperature: + 260 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.1.8
Read: Anytime
Write: Anytime
4.3.1.9
Read: Anytime
Write: Anytime
Freescale Semiconductor
Address: Module Base + 0x0008
Address: Module Base + 0x0009
LOW_ADDR[
LOW_ADDR[
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
18:11]
Field
Field
Field
10:3]
7–0
7–0
WP
7
W
W
R
R
WP
MPU Descriptor Register 2 (MPUDESC2)
MPU Descriptor Register 3 (MPUDESC3)
Memory range lower boundary address bits — The LOW_ADDR[18:11] bits represent bits [18:11] of the
global memory address that is used as the lower boundary for the described memory range.
Memory range lower boundary address bits — The LOW_ADDR[10:3] bits represent bits [10:3] of the global
memory address that is used as the lower boundary for the described memory range.
Write-Protect bit — The WP bit causes the described memory range to be treated as write-protected. If this
bit is set every attempt to write in the described memory range causes an access violation.
0
0
7
7
NEX
0
0
6
6
Figure 4-10. MPU Descriptor Register 2 (MPUDESC2)
Figure 4-11. MPU Descriptor Register 3 (MPUDESC3)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 4-10. MPUDESC2 Field Descriptions
Table 4-11. MPUDESC3 Field Descriptions
Table 4-9. MPUDESC1 Field Descriptions
5
0
5
0
0
LOW_ADDR[10:3]
0
0
0
4
4
Description
Description
Description
0
1
3
3
Chapter 4 Memory Protection Unit (S12XMPUV1)
HIGH_ADDR[22:19]
2
0
2
1
0
1
1
1
0
1
0
0
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