EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 137

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

DS785UM1
5.1.6.2.1
5.1.6.2.2
After power-on-reset, the ARM Core is automatically in run mode.
Once in run mode, it is possible to move to the Standby state under these conditions:
When the SHena bit is set to 1 and the user reads the Standby register location
0x8093_000C, the EP93xx is forced to transition into the Standby state. After this transition,
the state controller will hold the Standby state before re-loading and allowing transition to the
Run state.
A write to the
However, the system will automatically come back to normal operation after new clock
settings take effect. The amount of time the EP93xx remains in the Standby state depends on
whether the PLL is enabled, or if the EP93xx is using the external clock. If the PLL is enabled,
the EP93xx will remain in Standby until the PLL is locked. If the EP93xx is in PLL bypass
mode (nBYP1 = 1), then the EP93xx will remain in the Standby state for One to two
16.384 kHz clock cycles. This is to ensure a minimum 'off' time. The 16.384 kHz clock,
derived from the 32.768 kHz clock, times how long the EP93xx remains in the Standby state.
When the EP93xx normally enters Standby mode, the SDRAM controller puts the external
SDRAM into self-refresh before disabling its clocks (see
8). This condition is only true if the refresh enable bit (RFSHEN) in the SDRAM controller is
• A read from the Standby register location 0x8093_000C when the SHena bit in the
• A write to the
"DeviceCfg"
Power-on-Reset Run
Run Standby Mode
Standby
"ClkSet1"
Read Standby register &
SHena = 1
register is set to 1. This triggers the system to enter STANDBY mode.
"ClkSet1"
Interrupt (if enabled) or
ClkSet1 register
Write to
return from ClkSet1
register will also trigger the system to go into Standby mode.
Figure 5-4. Power States and Transitions
register.
Copyright 2007 Cirrus Logic
Power on
Reset
Run
Any Enabled Interrupt
Read Halt register
& SHena = 1
“SDRAM Self Refresh” on page 13-
Halt
EP93xx User’s Guide
System Controller
5-11
5