EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 492

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

12
PCCommon
12-14
Static Memory Controller
EP93xx User’s Guide
WC
31
15
Address: 0x8008_0024 - Read/Write
Default: 0x0000_0000
Definition: PC Card Common register
Bit Descriptions:
30
14
RSVD
29
13
28
12
HA:
PA:
RSVD:
WC:
AC:
RSVD
27
11
26
10
HC
Copyright 2007 Cirrus Logic
25
9
The data strobe assertion time is specified by (AA+1)
HCLK cycles. For example, if AA = 0x10, the data strobe
assertion time is 16 + 1 = 17 cycles of HCLK
Attribute space Hold time - Read/Write
The value written to this field specifies the minimum
‘number of HCLK cycles, minus 1’ between de-asserting
the data strobe, MCDAENn
strobe, MCADENn.
The Hold time is specified by (HA +1) HCLK cycles. For
example, if HA = 0xC, the Hold time is 12 + 1 = 13 cycles
of HCLK.
Attribute space setup time - Read/Write
The value written to this field specifies the ‘number of
HCLK cycles, minus 1’ that the address strobe,
MCADENn, is set up before assertion of the data strobe,
MCDAENn.
The Setup time is specified by (PA+1) HCLK cycles. For
example, if PA = 0x25, the Setup time is 37 + 1 = 38 cycles
of HCLK.
Reserved - Unknown During Read
Common Space Width - Read/Write
The value written to this bit specifies the bus-width of the
Common space:
0 - 8-bit wide Common space
1 - 16-bit wide Common space
Common Space Access time - Read/Write
24
8
23
7
22
6
21
5
,
and de-asserting the address
20
4
AC
PC
19
3
18
2
17
1
DS785UM1
16
0