EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 719

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

DS785UM1
23.5.8 Motorola SPI Format with SPO=0, SPH=1
SFRMOUT /
SFRMIN
SCLKOUT /
SCLKIN
The transfer signal sequence for Motorola SPI format with SPO=0, SPH=1 is shown in
Figure
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SFRMOUT master signal being driven LOW. The master
SSPTXD output pad is enabled. After a further one half SCLKOUT period, both master and
slave valid data is enabled onto their respective transmission lines. At the same time, the
SCLKOUT is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the
SCLKOUT signal.
In the case of a single word transfer, after all bits have been transferred, the SFRMOUT line
is returned to its idle HIGH state one SCLKOUT period after the last bit has been captured.
For continuous back-to-back transfers, the SFRMOUT pin is held LOW between successive
data words and termination is the same as that of the single word transfer.
SSRXD
SSTXD
SSPOE
• the SCLKOUT signal is forced LOW
• SFRMOUT is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
• when the SSP is configured as a master, the SSPCTLOE line is driven LOW, enabling
• when the SSP is configured as a slave, the SSPCTLOE line is driven HIGH, disabling
the SCLKOUT pad (active LOW enable)
the SCLKOUT pad (active LOW enable).
23-5, which covers both single and continuous transfers.
Q
Figure 23-5. Motorola SPI Frame Format with SPO=0 and SPH=1
M SB
MS B
Copyright 2007 Cirrus Logic
4 t o 16 bi t s
Synchronous Serial Port
EP93xx User’s Guide
LS B
LS B
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