EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 685

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

I
I2SGlSts
DS785UM1
2
rx0_fifo
21.7.4 I
_full
S Global Status Registers
31
15
RSVD
Address:
Default:
Definition:
Bit Descriptions:
tx0_fifo
empty
_half_
30
14
2
S Global Status Registers
o_half_
tx0_fifo
_empty
rx2_fif
full
29
13
rx2_fifo
_empty
tx0_fifo
_full
28
12
0x8082_0008 - Read/Write
0x0001_2492
UART Data Register
RSVD:
Tx0_underflow:
Tx1_underflow:
Tx2_underflow:
Rx0_overflow:
Rx1_overflow:
Rx2_overflow:
Tx0_overflow:
underflow
rx2_fifo_f
Rx2_
27
ull
11
underflow
tx2_fifo_h
empty
Rx1_
alf_
26
10
Copyright 2007 Cirrus Logic
tx2_fifo_e
underflow
mpty
Rx0_
25
9
Reserved. Unknown During Read.
when = 1, TX0 FIFO has underflowed.
when = 1, TX0 FIFO has underflowed.
when = 1, TX0 FIFO has underflowed.
when = 1, RX0 FIFO has overflowed and the FIFO pointer
is currently pointing at the last data received before the
overflow occurred.
when = 1, RX1 FIFO has overflowed and the FIFO pointer
is currently pointing at the last data received before the
overflow occurred.
when = 1, RX2 FIFO has overflowed and the FIFO pointer
is currently pointing at the last data received before the
overflow occurred.
when = 1, the tx0 FIFO is full and an attempt has been
made to write data to it by the APB or DMA. This bit is
cleared by writing a 0 to it.
tx2_fifo_
overflow
Tx2_
full
24
8
overflow
rx1_fifo
_half_
Tx1_
full
23
7
overflow
rx1_fifo
_empty
Tx0_
22
6
overflow
rx1_fifo
Rx2_
_full
21
5
tx1_fifo_
overflow
empty
half_
Rx1_
20
4
tx1_fifo_
overflow
empty
Rx0_
19
3
EP93xx User’s Guide
underflow
tx1_fifo_f
Tx2_
ull
18
2
I
2
S Controller
rx0_fifo_h
underflow
Tx1_
alf_
full
17
1
21-29
rx0_fifo_e
underflow
mpty
Tx0_
16
0
21