EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 612

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

17
17-16
17.5.1.2.1 Address Field
17.5.1.2.2 Control Field
17.5.1.2.3 Data Field
17.5.1.2.4 CRC Field
IrDA
EP93xx User’s Guide
The preamble, start and stop flags are a mixture of symbols which contain either 0, 1, or 2
pulses within the four time slots. Symbols with 0 and 2 pulses are used to construct flags
since they represent invalid data bit pairings (one pulse required per symbol to represent one
of four bit pairs). The preamble contains sixteen repeated transmissions of the four symbols:
1000 0000 1010 1000, the start flag contains one transmission of eight symbols: 0000 1100
0000 1100 0110 0000 0110 0000 and the stop flag contains one transmission of eight
symbols: 0000 1100 0000 1100 0000 0110 0000 0110. The address, control, data and CRC-
32 all use the standard 4PPM DDs described above.
The 8 bit address field is used by a transmitter to target a select group of receivers when
multiple stations are connected to the same set of serial lines. The address allows up to 255
stations to be uniquely addressed (00000000b to 11111110b). The global address
(11111111b) is use to broadcast messages to all stations. Serial port 1 contains an 8 bit
register which is used to program a unique address for broadcast recognition as well as a
control bit to enable/disable the address match function. Note that the address of received
frames is stored in the receive buffer along with normal data and that it is transmitted and
received starting with its LSB and ending with its MSB.
The IPC control field is 8 bits and is optional (as defined by the user). The FIR does not
provide any hardware decode support for the control byte, but instead treats all bytes
between the address and the CRC as data. Note that the control field is transmitted and
received starting with its LSB and ending with its MSB.
The data field can be any length which is a multiple of 8 bits, from 0 to 2045 bytes. The user
determines the data field length according to the application requirements and transmission
characteristics of the target system. Usually a length is selected which maximizes the amount
of data which can be transmitted per frame, while allowing the CRC checker to be able to
consistently detect all errors during transmission. Note that the serial port does not contain
any hardware which restricts the maximum amount of data transmitted or received. It is up to
the user to maintain these limits. If a data field which is not a multiple of 8 bits is received an
abort is signalled. Also note that each byte within the data field is transmitted and received
starting with its LSB and ending with its MSB.
The FIR uses the established 32 bit cyclical redundancy check (CRC-32) to detect bit errors
which occur during transmission. A 32 bit CRC is computed using the address, control and
data fields and is included in each frame. A separate CRC generator is implemented in both
the transmit and receive logic. The transmitter calculates a CRC while data is actively
transmitted byte shifting each byte transmitted through its serial shifter LSB first, then places
the inverse of the resultant 32 bit value at the end of each frame before the flag is transmitted.
In a similar manner, the receiver also calculates a CRC for each received data frame and
compares the calculated CRC to the expected CRC value contained within the end of each
received frame. If the calculated value does not match the expected value, an interrupt is
Copyright 2007 Cirrus Logic
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