EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 217
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 217 of 824
- Download datasheet (13Mb)
DS785UM1
7.4.12 Color Mode Definition
7.4.12.1 Pixel Look-up Table Mode
7.4.12.2 Triple 8-bit Color Definition Mode
7.4.12.3 16-bit 565 Color Definition Mode
7.4.12.4 16-bit 555 Color Definition Mode
1110 - Dim 888 Blinking:
1111 - Bright 888 Blinking:
One of four modes may be selected to define pixel color: Pixel Look-Up Table Mode, Triple 8-
Bit Mode, 16-Bit 565 Mode, and 16-Bit 555 Mode.
The Raster Engine contains a 256 x 24 bit RAM that is used as pixel look-up-table (LUT) for
pixel depths up to 8-bits. Appropriate blink operations, if any, are performed on the pixel data
fetched from the video memory and the resulting pixel data value is used as an index into the
LUT. The pixel value located at the index position continues through the video pipeline.
The LUT is memory mapped and may be written at any time. However, if it is written during a
non-blanking interval, the display may be momentarily corrupted.
Writing 0x0 to the C[3:0] bits (color bits) in the PixelMode register to 0x0 enables the LUT.
The 24 bits of data is divided into three color planes, where the RED, GREEN, and BLUE
each have 8 bits of color definition.
The 16 bits of data is divided into three color planes, where the RED and BLUE each have 5
bits for color definition and the GREEN has 6 bits for color definition.
The 16 bits of data is divided into three color planes, where the RED, GREEN, and BLUE
each have 5 bits of color definition. The MSB of the 16-bit data is not used.
of the 8 bit values is treated as a single value, and the blinking rules defined for the Dim
Single Blinking mode are applied.
of the 8 bit values is treated as a single value, and the blinking rules defined for the
Bright Single Blinking mode are applied.
The 24 bits of data is made up of three 8-bit values that represent the RGB colors. Each
The 24 bits of data is made up of three 8-bit values that represent the RGB colors. Each
1. The MSB is dropped
2. The remaining bits are shifted left by one
3.The LSB is set to ‘1’
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7-35
7
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