EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 307

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

DS785UM1
9.1.3 Packet Transmission Process
9.1.3.1 Carrier Deference
This section explains the complete packet transmission process as seen on the Ethernet line.
This process includes: carrier deference, back-off, packet transmission, transmission of EOF,
and SQE test. Refer to
The Ethernet/ISO/IEC 8802-3 topology is a single shared medium with several stations. Only
one station can transmit at a time. The access method is called Carrier Sense Multiple
Access with Collision Detection (CSMA/CD). This method is a “listen before talk” mechanism
that has an added feature to end transmissions when two, or more, stations start
transmissions at nearly the same time.
The CSMA portion of this method provides collision avoidance. Each station monitors its
receiver for carrier activity. When activity is detected, the medium is busy, and the MAC
defers (waits) until the medium no longer has a carrier.
Refer to
layer immediately moves to the Carrier Deference State Diagram. The Carrier Deference
state is independent of entry into the state diagram. The MAC layer may enter the state
diagram in any of its five states. The MAC layer exits the Carrier Deference only from the IFG
Transmission
Complete
Report Applicable
Figure
Transmit EOF
Transmit
Status
Start of Transmit
Transmission
Frame in fifo
Deference
9-4. Once sufficient bytes have been written to the transmit FIFO, the MAC
Carrier
Transmit JAM
Figure
There was
a collision
Figure 9-3. Packet Transmission Process
Carrier Deference is
detailed in the next diagram.
Transmission ends with
either completion of the
frame, or a collision.
Copyright 2007 Cirrus Logic
9-3.
The Packet Transmission Process
Report Applicable
Collision
Transmit
Status
Late
?
YES
NO
Report Applicable
The maximum number of
collisions is either 16 or 1
depending on the Onecoll bit
in the transmit descriptor.
number of
Collisions
Transmit
Status
Max
1/10/100 Mbps Ethernet LAN Controller
?
YES
NO
Wait for the duration
of the BackOff Timer
The backoff time is a computed
random number based on either
the standard algorithm or the
modified back-off algorithm.
See the ModBackoffE bit
in TxCTL.
EP93xx User’s Guide
9-5
9