EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 381

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

Descriptor Processor Transmit Registers
TXDQBAdd
DS785UM1
31
15
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
Address:
Chip Reset:
Soft Reset:
Definition:
30
14
29
13
28
12
0x0000_0000
Unchanged
Receive Header Length register. The Receive Header Length registers are
used to generate status after receiving a specific portion of a receive frame.
When the number of bytes specified in either register has been transferred to
the external data buffer, an appropriate status is generated. The status for a
receive header will reflect the number of bytes transferred for the current
frame, the address match field will be valid, and the other status bits will be set
to zero. A status will only be generated for header length 2 if the length is
greater than that specified for header length 1.
RSVD:
RHL2:
RHL1:
0x8001_00B0 - Read/Write
0x0000_0000
Unchanged
Transmit Descriptor Base Address register. The Transmit Descriptor Queue
Base Address defines the system memory address of the transmit descriptor
queue. This address is used by the MAC to reload the Transmit Current
Descriptor Address whenever the end of the descriptor queue is reached. The
base address should be set at initialization time and must be set to a word
aligned memory address.
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Receive Header Length 2.
Receive Header Length 1.
24
8
TDBA
TDBA
23
7
22
6
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
19
3
EP93xx User’s Guide
18
2
17
1
16
9-79
0
9