EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 769
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 769 of 824
- Download datasheet (13Mb)
DS785UM1
Address:
Default:
Definition:
Bit Descriptions:
0x808F_0000
0x0000_0000
Key scan initialization register.
RSVD:
DBNC:
DIS3KY:
DIAG:
BACK:
T2:
NA:
Copyright 2007 Cirrus Logic
Reserved. Unknown during read.
De-bounce start count. This value is used to pre-load the
de-bounce counter. The de-bounce counter counts the
number of consecutive scans that decoded the same
keys. Terminal count for the de-bounce counter is 0xFF.
Terminal count indirectly generates a key scan interrupt. A
pre-load value of 0xFC will cause the key scan circuitry to
count 3 identical consecutive keypad scans.
Disable 3 Key reset. Setting this bit high disables the three
key reset output to the watchdog reset block. Setting it
back low re-enables it.
Key scan diagnostic mode. Setting this bit high allows key
scanning to be directly controlled through the key register
by writes from the ARM Core. The DIAG.KEY[5:0] value is
written by the ARM Core. Then the KeyRegister.K bit is
read to determine if there is a key press. The result from
reading the KeyRegister.K bit is not hardware de-bounced.
Key scan back driving enable. Setting this bit high enables
the key scanning logic to back drive the row and column
pins of the chip high during the first two column counts in
the row/column counter.
Test mode bit. When this bit is set to “1”, the counter
RC_COUNT is advanced by 8 counts when EN is active.
The effect is that only column 0 is checked in each row.
This test mode allows a faster test of the ROW pins.
Not Assigned. These bits will read back the value written.
EP93xx User’s Guide
Keypad Interface
26-7
26
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