EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 627
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 627 of 824
- Download datasheet (13Mb)
SIRTR0
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
DMAERR:
TXDMAE:
RXDMAE:
0x808B_0030 - Read/Write
0x0000_0000, except that bit 4 is unknown at reset
IrDA Slow InfraRed Test Register 0.
RSVD:
SIREN:
SIROUT:
TXD:
RXD:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the IrDA receive section. If “1”,
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include framing errors, receive
abort, and CRC mismatch.
TX DMA interface enable. Setting to “1” enables the
private DMA interface to the transmit FIFO.
RX DMA interface enable. Setting to “1” enables the
private DMA interface to the receive FIFO.
Reserved. Unknown During Read.
The state of the SIREN after synchronization. Read only.
The state of SIROUT output from the InfraRed block. Read
only.
The state of the TXD input to the InfraRed block from
UART2. Read only.
The state of the RXD output from the InfraRed block to
UART2. Read only.
24
8
RSVD
SIREN
23
7
SIROUT
22
6
TXD
21
5
RXD
20
4
SIRT
19
3
EP93xx User’s Guide
SIRIN
18
2
S16CLK
17
1
TSIRC
17-31
IrDA
16
0
17
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